1. Field of the invention
The present invention relates to gate oxides of a semiconductor wafer, and more particularly, to a method for preventing gate oxides of a semiconductor wafer from being damaged by electromagnetic waves or particles generated in a plasma-related process.
2. Description of the prior art
A gate oxide is the most important component of a MOS (metal-oxide-semiconductor) transistor. The quality of the gate oxide will affect operations of the MOS transistor and the reliability of a semiconductor. However, a nicely formed gate oxide may be damaged during subsequent processes of a semiconductor process. In the example of a dry etching process, the potential difference generated by a plasma chamber of a dry etching machine may damage semiconductor devices through conducting materials. This is called plasma damage, and the gate oxide may be damaged in this process.
Please refer to FIG. 1 and FIG. 2. FIG. 1 is a cross-sectional view of a gate oxide of a prior art semiconductor wafer 11. FIG. 2 is a cross-sectional view of a gate oxide of another prior art semiconductor wafer 13 with via holes 22. When devices of the semiconductor wafer 11 are formed, a plurality of patterned gate oxides 10 and poly-silicon layers 12 are positioned on a substrate 14 of the semiconductor wafer 11 for functioning as MOS transistors or MOS capacitors. Theses devices are positioned separately and have to be connected through a backend device connection process. The backend device connection process is performed by depositing inter layer dielectrics (ILD) 16 to isolate the electrical connections between the devices, forming a device contacting hole 20 on the ILD 16 to delineate a region of the electrical connection between the layers, and depositing and patterning a conducting layer 24 such as metal 1 or metal 2 to perform the electrical connection. FIG. 2 shows that the connection process further comprises depositing inter metal dielectrics (IMD) 18 and forming a via hole (VIA) 22 on the IMD 18.
Generally, forming the contacting hole 20 on the ILD 16, forming the VIA 22 on the IMD 18, and patterning the conducting layer 24 are all performed by a dry etching process. The dry etching process is performed by removing substances on the surface of the semiconductor wafer through an ionic reaction. It is initiated by depositing ions from a plasma chamber. Because ion concentration of the plasma chamber is not exactly uniform, when ions are deposited onto the semiconductor wafer, they are not evenly distributed on the surface of the semiconductor wafer, their contacts with different conducting layers 24 below the photoresist 26 will form a potential difference on the semiconductor wafer. The potential difference between different conducting layers 24 will cause a voltage stress among the poly-silicon layers 12 by way of electrical connections through the contacting holes 20, via holes 22, and conducting layers 24. When the potential difference reaches a threshold voltage, current is generated and flows through the gate oxide 10 and the substrate 14 to reduce the potential difference. The arrow with a dotted line shows the current flowing through the gate oxides 10 and the substrate 14. Because the current flows through the gate oxides 10, it will cause damage to the gate oxides and the damage is a form of plasma damage.
Moreover, other factors in the plasma chamber may also damage the devices of the semiconductor wafer. For example, electromagnetic waves generated by the plasma chamber or material waves generated by movements of particles will penetrate into the ILD 16 through the space 25 between the conducting layers 24 and cause diffraction or interference to occur thus damage the gate oxides 10.
As the conducting layers 24 are distributed more closely, the space 25 is becoming narrower. Thus, the impact of the diffraction or interference is greatly enhanced such that they may cause serious damages to the gate oxides 10. Although methods of preventing the damages are urgently needed, they are often neglected.